A known semiconductor memory device which is fabricated on a semiconductor substrate is illustrated in FIG. 1. The prior-art semiconductor memory device comprises a memory cell array 1 having a plurality of memory cells arranged in rows and columns, a row address buffer circuit 2 temporarily storing a row address signal AX consisting of a plurality of bits, a row address decoder circuit 3 decoding the row address signal AX supplied from the row address buffer circuit 2, and a plurality of word lines WL1 and WL2 extending in row direction. Each of the memory cells in the memory cell array 1 has a circuit arrangement shown in FIG. 2. All of the memory cells are similar in circuit arrangement to one another so only one memory all will be described in detail.
The memory located at the upper end of the left side comprises a pair of load resistors 4 and 5 each connected at one of the ends thereof to a source of positive voltage Vcc, a pair of n-channel type memory transistors 6 and 7 having source-drain paths respectively coupled between the other ends of the load resistors 4 and 5 and the ground terminal and gate electrodes respectively coupled to the other ends of the load resistors 5 and 4, and a pair of n-channel type transfer gate transistors 8 and 9 having source-drain paths respectively coupled between the other ends of the load resistors 4 and 5 and a pair of bit lines D0 and DB0 and gate electrodes coupled to the word line WL1. The other ends of the load resistors 4 and 5 serve as memory nodes, the voltage levels of which represent either logic "0" or logic "1". The gate electrodes of the transfer gate transistors 8 and 9 are thus coupled to the word line WL1 so that the memory nodes 10 and 11 are electrically connected to the bit lines D0 and DB0 through the transfer gate transistors 8 and 9 upon activation of word line WL1 by means of the row address decoder circuit 3. As described in U.S.P. 3,539,839, it is necessary to select the memory transistors 6 and 7 larger in on-resistance than the transfer gate transistors 8 and 9 so as to prevent the data bit stored therein from destruction. For this reason, each of the memory transistors 6 and 7 and each of the transfer gate transistors 8 and 9 have respective gate widths which are in the ratio 4 : 1.
The prior-art semiconductor memory device illustrated in FIG. 1 further comprises a column address buffer circuit 12 temporarily storing a column address signal AY consisting of a plurality of bits, a column address decoder circuit 13 operative to decode the column address signal AY supplied from the column address buffer circuit 12, plural pairs of bit lines D0 and DB0 and D1 and DB1 extending in a column direction and plural pairs of n-channel type transfer gate transistors 14, 15, 16 and 17. The bit lines D0 and DB0 are coupled at one of their ends to the source of positive voltage Vcc through load resistors 18 and 19, respectively, and at the other ends thereof to a pair of data lines DL and DBL through respective source-drain paths of the transfer gate transistors 14 and 15, respectively. Similarly, bit lines D1 and DB1 are coupled at one of their ends thereof to the source of positive voltage Vcc through load resistors 20 and 21, respectively, and at the other ends thereof to the data lines DL and DBL through respective source-drain paths of the transfer gate transistors 16 and 17, respectively. The data lines DL and DBL are coupled to a write-in circuit 22 and a read-out circuit 23 which in turn are respectively coupled to a data input terminal 24 and a data output terminal 25. The write-in circuit 22 and the read-out circuit 23 are selectively activated by a control circuit 26 depending upon the voltage level of a write enable signal WE.
In operation, when a new data bit is to be read out from the memory cell located at the upper end of the left side a control device such as a microprocessor provides a row address signal AX and a column address signal AY specifying the memory cell at the upper end of the left side. When the row address signal AX is stored in the row address buffer circuit 2, the row address decoder circuit 3 makes the word line WL1 go up to the active high voltage level Vcc, so that all of the transfer gate transistors coupled to the word line WL1 turn on. Then, the data bits stored in the memory cells appear on the respective bit line pairs in the form of complementary voltage levels. When the column address signal AY is stored in the column address buffer circuit 12, the column address decoder circuit 13 causes the transfer gate transistors 14 and 15 to turn on. Then, the data bit appearing on the bit line pair D0 and DB0 is transferred to the data lines DL and DBL. When the write enable signal WE is in the high level, the control circuit 26 activates the read-out circuit 23 so that the data bit read out from the memory cell at the upper end of the left side appears at the data output terminal 25 in the form of a single voltage level.
On the other hand, when a new data bit should be written into the memory cell at the upper end of the left side, a new data bit is supplied from the external device to the data input terminal 24. A row address signal AX and a column address signal AY similar to those supplied in the read-out mode, are supplied to address buffers 2 and 12, respectively. Then, the row address decoder circuit 3 causes the word line WL1 to go up to the active high level Vcc to turn on the transfer gate transistors coupled to the word line WL1, and the column address decoder circuit 13 causes the transfer gate transistors 14 and 15 to turn on to allow the data lines DL and DBL to electrically connect to the bit lines D0 and DB0. In the write-in mode, the write enable signal WE goes down to the active low level so that the write-in circuit 22 is activated. Upon appearance of a new data bit at the data input terminal, the write-in circuit 22 converts the new data bit into the complementary voltage levels which are put on the data lines DL and DBL. The transfer gate transistors 14 and 15 have already turned on so that the new data bit in the form of complementary voltage levels is transferred to the bit lines D0 and DB0. The new data bit transferred to the bit lines D0 and DB0 passes through the transfer gate transistors 8 and 9 and reaches the memory nodes 10 and 11. Upon storing the new data bit in the form of complementary voltage levels into the memory nodes 10 and 11, the memory transistors 6 and 7 may turn on and off in accordance with the new data bit. Namely, if the new data bit is equal in logic level to the previous data bit, the memory transistors 6 and 7 are not changed, but when the new data bit is different from the previous data bit, the memory transistors 6 and 7 may be shifted from the on-state to the off-state and vice versa, respectively.
Thus, the row address decoder circuit 3 incorporated in the prior-art semiconductor device causes one of the word lines to go up to the positive voltage level Vcc upon both of the write-in operation and the read-out operation. However, a problem is encountered in the prior-art semiconductor device in that each of the memory cells occupies a large amount of real estate on the semiconductor substrate. This is because of the fact that the memory transistors 6 and 7 have wide gate electrodes which are four times wider than those of the transfer gate transistors 8 and 9.